Tuning the conductance topology in solids
DOI
10.1063/5.0142721
Abstract
The inertia of trapping and detrapping of nonequilibrium charge carriers affects the electrochemical and transport properties of both bulk and nanoscopic structures in a very peculiar way. An emerging memory response with hysteresis in the current–voltage response and its eventual multiple crossing, produced by this universally available ingredient, are signatures of this process. Here, we deliver a microscopic and analytical solution for these behaviors, understood as the modulation of the topology of the current–voltage loops. Memory emergence thus becomes a characterization tool for intrinsic features that affect the electronic transport of solids such as the nature and number of trapping sites, intrinsic symmetry constraints, and natural relaxation time scales. This method is also able to reduce the seeming complexity of frequency-dependent electrochemical impedance and cyclic voltammetry observable for a variety of systems to a combination of simple microscopic ingredients.
Document Type
Article
Publication Date
4-3-2023
Publisher Statement
Published under an exclusive license by AIP Publishing
Recommended Citation
Victor Lopez-Richard, Rafael Schio Wengenroth Silva, Ovidiu Lipan, Fabian Hartmann; Tuning the conductance topology in solids. J. Appl. Phys. 7 April 2023; 133 (13): 134901. https://doi.org/10.1063/5.0142721